1. Field of the Invention
The present invention relates to a semiconductor device including MOS transistors (insulated gate field-effect transistors), and more specifically, it relates to a structure for improving the electrostatic damage resistance of an output circuit for externally outputting signals.
2. Description of the Prior Art
FIG. 20 schematically illustrates the structure of an output circuit employed in a general semiconductor device. Referring to FIG. 20, the output circuit includes an output drive circuit 900 for generating a signal to be outputted in accordance with an internal signal, and an output circuit final stage 902 for outputting a signal to an output node 904 in accordance with the output signal from the output drive circuit 900. The output node 904 is connected to an external pin terminal LP through a pad PD. The output circuit final stage 902 includes an n-channel MOS transistor N1 which is connected between a power supply node and the output node 904 and conducts, when the output signal from the output drive circuit 900 is at a high level, for driving the output node 904 to a power supply voltage VDD level, and an n-channel MOS transistor N2 which conducts, when the output signal from the output drive circuit 900 is at a high level, for discharging the output node 904 to the ground voltage level. Only one of these MOS transistors N1 and N2 conducts. In an output high impedance state, both of the MOS transistors N1 and N2 enter non-conducting states.
The output circuit final stage 902 is required to charge/discharge the output node 904 at a high speed. This output node 904 is connected to the external pin terminal LP through the pad PD, and the transistors N1 and N2 have relatively large current drivability due to the necessity for charging/discharging a large load at a high speed.
However, the output node 904 is connected to the external pin terminal LP through the pad PD, and equivalently connected with an LCR circuit formed by a high inductance component L, a parasitic capacitance C, wiring resistance and parasitic resistance R by wiring resistance of an external circuit. In case of charging/discharging such LCR circuit at a high speed, ringing is caused at the output node 904 and it takes a long time for stabilizing the output signal. In order to generate the output signal at a high speed with no ringing, the output circuit final stage 902 charges/discharges the output node 904 over a plurality of stages.
FIG. 21 illustrates an exemplary structure of a conventional multistage-drive output circuit final stage. This FIG. 21 shows a circuit part for discharging the output node 904. A circuit for pulling up the output node 904 to a high level may include a similar structure for multistage driving, appropriately depending on circuit characteristics of the output node 904 such as the dominance of overshoot or undershoot in the output node 904.
Referring to FIG. 21, n-channel MOS transistors N2a and N2b are provided in parallel between ground node and the output node 904. Conduction/non-conduction of MOS transistors N2a and N2b is controlled in accordance with control signals .phi.1 and .phi.2 respectively. In the structure of the conventional multistage-drive output circuit final stage, the n-channel MOS transistor N2 of the output circuit final stage 902 shown in FIG. 20 is split into the two MOS transistors N2a and N2b. These two MOS transistors N2a and N2b conduct at different timings, thereby preventing the output node 904 from rapid discharge. This discharge operation is now described with reference to a waveform diagram shown in FIG. 22.
The control signal .phi.1 first rises from a low level to a high level so that the MOS transistor N2a conducts for relatively slowly discharging the output node 904. Then, the control signal .phi.2 rises from a low level to a high level, so that the MOS transistor N2b conducts. Thus, the two MOS transistors N2a and N2b discharge the output node 904, so that the voltage of the output signal rapidly falls to a low level. The control signal .phi.2 is activated at such a time that no undershoot is caused even by the rapid fall of the output signal from the output node 904. The activation timings for the control signals .phi.1 and .phi.2 may be simply decided using a delay circuit, or activation of the control signal .phi.2 may be controlled in response to the voltage level of the output node 904. In any case, the MOS transistors N2a and N2b for discharging the output node 904 conduct at different timings, thereby preventing rapid discharge of the output node 904 at a relatively high voltage level with a large discharge current. Alternatively, the voltage level of the output node 904 may be first reduced by high-speed discharge, and then the output node 904 is discharged at a low speed. Thus, the output signal can be stabilized at a faster timing with no undershoot.
The output node 904 is connected to the external pin terminal LP through the pad PD. The external pin terminal LP is connected to an external environment. Electrostatic discharge may be caused in the output node 904 through the external pin terminal LP. The cause for such electrostatic discharge may be the human body, a package insertion apparatus, a system operation or thunder. Such electrostatic discharge in the output node 904 may result in damage of gate insulating films of the MOS transistors N1 and N2 of the output circuit final stage 902, or a large current flow (in amperes) caused by this electrostatic discharge may damage interconnection lines or P-N junctions. In order to prevent electrostatic discharge damage (ESD) caused by such electrostatic discharge, the output circuit final stage 902 must satisfy the specification value of ESD resistance. To this end, elements for improving the ESD resistance are added with respect to the output node 904.
FIG. 23 schematically illustrates the planar layout of the output circuit final stage shown in FIG. 21. Referring to FIG. 23, high-concentration N-type impurity regions 901, 902, 903, 904, 905 and 906 of low resistance are arranged alignedly with each other. Gate electrode layers 907 and 908 are arranged between the impurity regions 901 and 902 and between the impurity regions 902 and 903 respectively. Gate electrode layers 909 and 910 are arranged between the impurity regions 904 and 905 and between the impurity regions 905 and 906 respectively. The gate electrode layers 907 and 908 are connected to receive the control signal 41, and the gate electrode layers 909 and 910 are connected to receive the control signal .phi.2.
The impurity regions 901 and 903 are connected to the output node through contact holes CT, and the impurity region 902 is connected to a power supply node (ground node) through contact holes CT. The impurity regions 904 and 906 are connected to the output node through contact holes CT, and the impurity region 905 is connected to the power supply node (ground node) through contact holes CT.
The impurity regions 901, 902 and 903 and the gate electrode layers 907 and 908 form the MOS transistor N2a, and the impurity regions 904, 905 and 906 and the gate electrode layers 909 and 910 form the MOS transistor N2b. Two MOS transistors are connected in parallel with each other, to form each MOS transistor. Thus, a MOS transistor formed by the impurity regions 901 and 902 and the gate electrode layer 907 and that formed by the impurity regions 902 and 903 and the gate electrode layer 908 are connected in parallel with each other, thereby implementing the MOS transistor N2a having high current drivability.
In order to improve electrostatic damage resistance against electrostatic discharge on the output node (the output node 904 shown in FIG. 21) connected with the MOS transistors N2a and N2b, impurity regions 911 to 919 connected to the power supply node (ground node) through contact holes are so arranged as to enclose the impurity regions 901, 903, 904 and 906 connected to the output node. The impurity regions 911, 912 and 913 enclose the impurity region 901. The impurity regions 914, 915 and 916 enclose the impurity regions 903 and 904. The impurity regions 917, 918 and 919 enclose the impurity region 906. These additional impurity regions 911 to 919 are faced to the corresponding impurity regions 901, 903, 904 and 906 connected to the output node through thick field insulating films. These impurity regions 911 to 919 are connected to the power supply node. Thus, the additional impurity regions 911 to 919 form so-called field transistors with the corresponding impurity regions 901, 903, 904 and 906 connected to the output node.
FIG. 24 schematically illustrates the structure of a field transistor. Referring to FIG. 24, the field transistor includes high-concentration N-type impurity regions 921 and 922 formed spacedly on a surface of a P-type semiconductor substrate region 920, and a thick field insulating film 923 formed between these impurity regions 921 and 922. The impurity region 922 is connected to the output node 904, and the impurity region 921 is connected to the power supply node (ground node). When a positive voltage is applied to the output node 904 by electrostatic discharge, a lateral parasitic bipolar transistor formed by the impurity regions 921 and 922 and the substrate region 920 conducts by avalanche breakdown by a high electric field in the impurity region 922, to absorb electrostatic charges supplied to the output node 904. The impurity region 922 corresponds to the impurity regions 901, 903, 904 and 906 connected to the output node shown in FIG. 23, and the impurity region 921 corresponds to any of the additional impurity regions 911 to 919.
This field transistor absorbs an abnormal high voltage by turning-on of the lateral parasitic bipolar transistor resulting from avalanche breakdown in the impurity region 922. A ground line may be arranged on the field insulating film 923 as a gate electrode of an aluminum gate field transistor. In this case, a diode-connected MOS transistor having a large threshold voltage is equivalently connected to the output node 904, for absorbing a negative surge voltage applied thereto. In the field transistor having no gate electrode, the parasitic bipolar transistor conducts by a reverse-directional avalanche breakdown when a large negative surge voltage is applied to the output node 904, to absorb the abnormal negative surge voltage.
As shown in FIG. 23, the additional impurity regions 911 to 919 connected to the power supply node enclose the impurity regions 901, 903, 904 and 906 connected to the output node for forming a field transistor, thereby preventing the output node from electrostatic damage caused by electrostatic discharge.
As hereinabove described, the impurity regions connected to the power supply node are arranged to enclose the impurity regions connected to the output node, thereby forming a field transistor and improving the ESD resistance. The channel length of the field transistor is made not longer than 3 .mu.m, to implement high-speed response of turning-on of a parasitic bipolar transistor resulting from avalanche breakdown. In order to absorb a large current, the impurity regions 911 to 919 must have sufficient areas. The impurity regions 911 to 919 are connected in parallel with each other, to implement a large field transistor as a whole.
However, the impurity regions 911 to 919 must be arranged to enclose the output circuit final stage, and hence the occupying area of the output circuit final stage is disadvantageously increased. Particularly when a semiconductor memory device has a great data output bit number of 16 or 32, for example, the number of output circuits is increased accordingly, to remarkably hinder high integration.
Particularly when a similar field transistor is arranged for charging MOS transistors in addition to the field transistor for discharging MOS transistors, the occupying area of the output circuit final stage is further increased to extremely hinder high integration.